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64-position otp digital potentiometer ad5273 rev. h information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2002C2010 analog devices, inc. all rights reserved. features 64 positions one-time programmable (otp) 1 set-and-forget resistance settinglow cost alternative over eemem unlimited adjustments prior to otp activation 1 k, 10 k, 50 k, 100 k end-to-end terminal resistance compact 8-lead sot-23 standard package ultralow power: i dd = 5 a maximum fast settling time: t s = 5 s typical during power-up i 2 c-compatible digital interface computer software 2 replaces microcontroller in factory programming applications wide temperature range: ?40c to +105c low operating voltage: 2.7 v to 5.5 v otp validation check function applications system calibrations electronics level settings mechanical potentiometers and trimmer replacement automotive electronics adjustments transducer circuit adjustments programmable filters up to 6 mhz bw 3 general description the ad5273 is a 64-position, one-time programmable (otp) digital potentiometer 4 that employs fuse link technology to achieve permanent program setting. this device performs the same electronic adjustment function as most mechanical trimmers and variable resistors. it allows unlimited adjustments before permanently setting the resistance values. the ad5273 is programmed using a 2-wire, i 2 c-compatible digital control. during write mode, a fuse blow command is executed after the final value is determined, thereby freezing the wiper position at a given setting (analogous to placing epoxy on a mechanical trimmer). when the permanent setting is achieved, the value does not change, regardless of the supply variations or environ- mental stresses under normal operating conditions. to verify the success of permanent programming, analog devices, inc., patterned the otp validation such that the fuse status can be discerned from two validation bits in the read mode. functional block diagram gnd i 2 c interface and control logic a w b wiper register fuse link v dd ad0 sda scl ad5273 03224-001 figure 1. in addition, for applications that program the ad5273 at the factory, analog devices offers device programming software 2 running on windows? nt, windows 2000, and windows xp operating systems. this software application effectively replaces any external i 2 c controllers, which in turn enhances the user systems time-to-market. the ad5273 is available in 1 k, 10 k, 50 k, and 100 k resistances and in a compact 8-lead sot-23 standard package. it operates from ?40c to +105c. along with its unique otp feature, the ad5273 lends itself well to general digital potentiometer applications due to its effective resolution, array resistance options, small footprint, and low cost. an ad5273 evaluation kit and software are available. the kit includes the connector and cable that can be converted for factory programming applications. for applications that require dynamic adjustment of resistance settings with nonvolatile eemem, users should refer to the ad523x and ad525x families of nonvolatile memory digital potentiometers. 1 otp allows unlimited adjustme nts before permanent setting. 2 analog devices cannot gua rantee the software to be 100% compatible to all systems due to the wide variatio n in computer configurations. 3 applies to 1 k parts only. 4 the terms digital potentiometer, vr, and rdac are used interchangeably.
ad5273 rev. h | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 4 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 8 ? theory of operation ...................................................................... 13 ? one-time programming ........................................................... 13 ? variable resistance and voltage for rheostat mode ............. 14 ? variable resistance and voltage for potentiometer mode .... 14 ? esd protection ........................................................................... 15 ? terminal voltage operating range .......................................... 15 ? power-up/power-down sequences ......................................... 15 ? power supply considerations ................................................... 15 ? controlling the ad5273 ................................................................ 16 ? software programming ............................................................. 16 ? i 2 c controller programming .................................................... 17 ? controlling two devices on one bus ..................................... 18 ? applications information .............................................................. 19 ? dac .............................................................................................. 19 ? programmable voltage source with boosted output ........... 19 ? programmable current source ................................................ 19 ? gain control compensation .................................................... 19 ? programmable low-pass filter ................................................ 20 ? level shift for different voltages operation .......................... 20 ? rdac circuit simulation model ............................................. 20 ? evaluation board ............................................................................ 21 ? outline dimensions ....................................................................... 22 ? ordering guide .......................................................................... 22 ? revision history 10/10rev. g to rev. h changes to otp power supply parameter in table 1 .................. 4 changes to v dd pin description in table 3................................... 7 changes to one-time programming section ............................ 13 changes to power supply considerations section, figure 38 .. 15 updated outline dimensions ....................................................... 22 changes to ordering guide .......................................................... 22 8/08rev. f to rev. g changes to power supplies parameter in table 1 ......................... 3 updated fuse blow condition to 400 ms throughout ............... 5 1/08rev. e to rev. f changes to table 1 ............................................................................ 4 changes to table 2 ............................................................................ 6 changes to table 3 ............................................................................ 7 inserted figure 28 ........................................................................... 12 changes to one-time programming section ............................ 13 changes to power supply considerations section ..................... 15 deleted figure 35 ............................................................................ 15 changes to figure 36 ...................................................................... 15 updated outline dimensions ....................................................... 22 changes to ordering guide .......................................................... 22 1/05rev. d to rev. e changes to features .......................................................................... 1 changes to specifications ................................................................. 3 changes to table 3 ............................................................................. 6 changes to power supply considerations section .................... 15 changes to figure 35 and figure 37............................................. 15 changes to dac section ............................................................... 19 changes to level shift for different voltages operation section........................................................................... 20 deleted the resistance scaling section ....................................... 20 deleted the resolution enhancement section ........................... 20 12/04rev. c to rev. d updated format .................................................................. universal changes to specifications ................................................................. 3 changes to theory of operation section.................................... 13 changes to power supply consideration s section .................... 15 changes to figure 35, figure 36, and figure 37 ......................... 15 11/03rev. b to rev. c changes to sda bit definitions and descriptions .................... 10 changes to one-time programming (otp) section................ 11 changes to table iii ....................................................................... 11 changes to power supply considerations .................................. 13 changes to figure 8, figure 9, and figure 10 ............................. 13
ad5273 rev. h | page 3 of 24 10/03rev. a to rev. b changes to features .......................................................................... 1 changes to applications ................................................................... 1 changes to specifications ................................................................. 2 changes to absolute maximum ratings ........................................ 4 changes to pin function descriptions ........................................... 5 changes to tpc 7, tpc 8, tpc 13, and tpc 14 captions ......... 7 deleted tpc 20; renumbered successive tpcs ........................... 9 change to tpc 21 caption .............................................................. 9 change to the sda bit definitions and descriptions ................ 10 replaced theory of operation section ........................................ 11 replaced determining the variable resistance and voltage section ................................................................................ 11 replaced esd protection section ................................................. 12 replaced terminal voltage operating range section ............... 12 replaced power-up sequence section ......................................... 12 replaced power supply considerations section ......................... 13 changes to application section .................................................... 16 change to equation 9 ..................................................................... 17 deleted digital potentiometer family selection guide ............. 19 6/03rev. 0 to rev. a change to specifications .................................................................. 2 change to power supply considerations section ....................... 12 updated outline dimensions ........................................................ 20 12/02revision 0: initial version
ad5273 rev. h | page 4 of 24 specifications v dd = 2.7 v to 5.5 v, v a < v dd , v b = 0 v, ?40c < t a < +105c, unless otherwise noted. table 1. parameter symbol test conditions/comments min typ 1 max unit dc characteristicsrheostat mode resolution n 6 bits resistor differential nonlinearity 2 r-dnl 10 k, 50 k, 100 k r wb , v a = nc ?0.5 +0.05 +0.5 lsb 1 k r wb , v a = nc ?1 +0.25 +1 lsb resistor nonlinearity 2 r-inl 10 k, 50 k, 100 k r wb , v a = nc ?0.5 +0.10 +0.5 lsb 1 k r wb , v a = nc ?5 +2 +5 lsb nominal resistance tolerance 3 r ab /r ab t a = 25c 10 k, 50 k, 100 k ?30 +30 % nominal resistance, 1 k r ab 0.8 1.2 1.6 k rheostat mode temperature coefficient 4 (r ab /r ab )/?t wiper = nc 300 ppm/c wiper resistance r w i w = v dd /r, v dd = 3 v or 5 v 60 100 dc characteristicspotentiometer divider mode differential nonlinearity 5 dnl ?0.5 +0.1 +0.5 lsb integral nonlinearity 5 inl ?0.5 +0.5 lsb voltage divider 4 temperature coefficient (v w /v w )/t code = 0x20 10 ppm/c full-scale error v wfse code = 0x3f ?1 0 lsb 10 k, 50 k, 100 k ?1 0 lsb 1 k ?6 0 lsb zero-scale error v wzse code = 0x00 ?6 0 lsb 10 k, 50 k, 100 k 0 1 lsb 1 k 0 5 lsb resistor terminals voltage range 6 v a , v b , v w gnd v dd v capacitance 7 a, b c a , c b f = 5 mhz, measured to gnd, code = 0x20 25 pf capacitance 7 w c w f = 1 mhz, measured to gnd, code = 0x20 55 pf common-mode leakage i cm v a = v b = v w 1 na digital inputs and outputs input logic high (sda and scl) 8 v ih 0.7 v dd v dd + 0.5 v input logic low (sda and scl) 8 v il ?0.5 0.3 v dd v input logic high (ad0) v ih 3.0 v dd v input logic low (ad0) v il v in = 0 v or 5 v 0 0.4 v input logic current i il 0.01 1 a input capacitance 7 c il 3 pf output logic low (sda) v ol 0.4 v three-state leakage current i oz 1 a output capacitance 7 c oz 3 pf power supplies power supply range v dd 2.7 5.5 v otp power supply 8 , 9 v dd_otp t a = 25c 1 k (dd8), 10 k (dd9) 5.0 5.25 5.5 v 50 k (dyg), 100 k (dyh) 4.75 5.0 5.25 v supply current i dd v ih = 5 v or v il = 0 v 0.1 5 a otp supply current 8 , 10 , 11 i dd_otp t a = 25c, v dd_otp = 5 v 100 ma
ad5273 rev. h | page 5 of 24 parameter symbol test conditions/comments min typ 1 max unit power dissipation 12 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 0.5 27.5 w power supply sensitivity psrr r ab = 1 k ?0.3 +0.3 %/% psrr r ab = 10 k, 50 k, 100 k ?0.05 +0.05 %/% dynamic characteristics 7, 13, 14 bandwidth, ?3 db bw_1 k r ab = 1 k, code = 0x20 6000 khz bw_10 k r ab = 10 k, code = 0x20 600 khz bw_50 k r ab = 50 k, code = 0x20 110 khz bw_100 k r ab = 100 k, code = 0x20 60 khz total harmonic distortion thd w v a = 1 v rms, r ab = 1 k, v b = 0 v, f = 1 khz 0.05 % adjustment settling time t s1 v a = 5 v 1 lsb error band, v b = 0 v, measured at v w 5 s power-up settling time after fuses blown t s2 v a = 5 v 1 lsb error band, v b = 0 v, measured at v w , v dd = 5 v 5 s resistor noise voltage e n_wb r ab = 1 k, f = 1 khz, code = 0x20 3 nv/hz interface timing characteristics 7, 14, 15 applies to all parts scl clock frequency f scl 400 khz t buf bus free time between stop and start t 1 1.3 s t hd; sta hold time (repeated start) t 2 after this period, the first clock pulse is generated 0.6 s t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 50 s t su; sta setup time for start condition t 5 0.6 s t hd; dat data hold time t 6 0.9 s t su; dat data setup time t 7 0.1 s t f fall time of both sda and scl signals t 8 0.3 s t r rise time of both sda and scl signals t 9 0.3 s t su; sto setup time for stop condition t 10 0.6 s otp program time t 11 400 ms 1 typical values represent av erage readings at 25c, v dd = 5 v, and v ss = 0 v. 2 resistor position nonlinearity error, r-inl, is the deviatio n from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. 3 v ab = v dd , wiper (v w ) = no connect. 4 ?r wb /?t = ?r wa /?t. temperature coefficient is code-dependent; see the typical performance characteristics section. 5 inl and dnl are measured at v w . inl with the rdac configured as a potentiometer divider similar to a voltage output dac. v w with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 ls b maximum are guaranteed monotonic operating conditions. 6 the a, b, and w resistor terminals have no limitations on polarity with respect to each other. 7 guaranteed by design; not subject to production test. 8 the minimum voltage re quirement on the v ih is 0.7 v dd . for example, v ih min = 3.5 v when v dd = 5 v. it is typical for the scl and sda resistors to be pulled up to v dd . however, care must be taken to ensure that the minimum v ih is met when the scl and sda are driven directly from a low voltage logic controller without pull-up resistors. 9 different from the operating power supply; the power supply for otp is used one time only. 10 different from the operating current; the supply current for otp lasts approximately 400 ms for the one t ime it is needed. 11 see figure 28 for the energy plot during the otp program. 12 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 13 bandwidth, noise, and settling time depend on the terminal resistance value chosen. the lowest r value results in the fastest settling time and highest bandwidth. the highest r value results in the minimum overall power consumption. 14 all dynamic characteristics use v dd = 5 v. 15 see figure 29 for the location of the measured values.
ad5273 rev. h | page 6 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 2. parameter rating v dd to gnd ?0.3 v +6.5 v v a , v b , v w to gnd gnd, v dd maximum current i wb , i wa pulsed 20 ma i wb continuous (r wb 1 k, a open) 1 4 ma i wa continuous (r wa 1 k, b open) 4 ma digital input and output voltage to gnd 0 v, v dd operating temperature range ?40c to +105c maximum junction temperature (t j max) 150c storage temperature ?65c to +150c reflow soldering peak temperature 260c time at peak temperature 20 sec to 40 sec thermal resistance ja , sot-23 2 230c/w 1 maximum terminal current is boun ded by the maximum current handling of the switches, the maximum power di ssipation of the package; the maxi- mum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 package power dissipation = (t j max C t a )/ ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5273 rev. h | page 7 of 24 pin configuration and fu nction descriptions w 1 v dd 2 gnd 3 scl 4 a 8 b 7 ad0 6 sda 5 ad5273 top view (not to scale) 03224-002 figure 2. pin configuration table 3. pin function descriptions pin no. mnemonic description 1 w wiper terminal w. gnd v w v dd . 2 v dd positive power supply. specified for non-otp operation from 2.7 v to 5.5 v. for otp programming, v dd_otp must be set within the window of 5 v to 5.5 v for the 1 k (dd8) and 10 k ( dd9) options, or within the window of 4.75 v to 5.25 v for the 50 k (dyg) and 100 k (dyh) options, and be capable of sourcing 100 ma. 3 gnd common ground. 4 scl serial clock input. requires a pull-up resistor. if it is driven directly from a logic controller without the pull-up resistor, ensure that the v ih minimum is 0.7 v dd . 5 sda serial data input/output. requires a pull-up resistor. if it is driven directly from a logic controller without the pull-up resistor, ensure that the v ih minimum is 0.7 v dd . 6 ad0 i 2 c device address bit. allows a maximum of two ad5273 devices to be addressed. 7 b resistor terminal b. gnd v b v dd . 8 a resistor terminal a. gnd v a v dd .
ad5273 rev. h | page 8 of 24 typical performance characteristics v dd = 3v v dd = 5v code (decimal) 0.5 0.3 ?0.5 06 4 code (decimal) 0.10 0.06 ?0.10 06 8 potentiometer mode dnl (lsb) 16 24 32 40 48 56 0.02 ?0.02 ?0.06 8 rheostat mode inl (lsb) 16 24 32 40 48 56 0.1 ?0.1 ?0.3 4 03224-006 r ab = 10k t a = +85 c t a = +25 c t a = +125 c t a = ?40 c r ab = 10k t a = 25 c 03224-003 figure 3. r inl vs. code vs. supply voltages figure 6. dnl vs. code vs. temperature code (decimal) 0.25 0.15 ?0.25 06 4 code (decimal) 0.10 0.06 ?0.10 06 8 potentiometer mode inl (lsb) 16 24 32 40 48 56 0.02 ?0.02 ?0.06 4 03224-007 r ab = 10k t a = 25 c 3v 5v 8 rheostat mode dnl (lsb) 16 24 32 40 48 56 0.05 ?0.05 ?0.15 03224-004 r ab = 10k t a = 25 c v dd = 5v v dd = 3v figure 4. r dnl vs. code vs. supply voltages figure 7. inl vs. code vs. supply voltages code (decimal) 0.10 0.06 ?0.10 06 4 code (decimal) 0.10 0.06 ?0.10 06 8 potentiometer mode dnl (lsb) 16 24 32 40 48 56 0.02 ?0.02 ?0.06 4 03224-008 r ab = 10k t a = 25 c 3v 5v 8 potentiometer mode inl (lsb) 16 24 32 40 48 56 0.02 ?0.02 ?0.06 03224-005 r ab = 10k t a = +85 c t a = +25 c t a = +125 c t a = ?40 c figure 5. inl vs. code vs. temperature figure 8. dnl vs. code vs. supply voltages
ad5273 rev. h | page 9 of 24 6 1234 5 supply voltage (v) 0.025 0.020 0 0 potentiometer mode linearity (lsb) 0.015 0.010 0.005 03224-009 t a = 25 c r ab = 10k code = 0x20 figure 9. inl vs. supply voltage supply voltage (v) 0.4 0.3 ?0.1 06 rheostat mode linearity (lsb) 1234 5 0.2 0.1 0 03224-010 t a = 25 c r ab = 10k code = 0x20 figure 10. r inl vs. supply voltage temperature ( c) 0 ?1.0 ?40 100 ?20 fse (lsb) 020406080 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 ?0.8 ?0.7 ?0.9 03224-011 r ab = 10k v dd = 3v v dd = 5v figure 11. full-scale error temperature ( c) 1.0 0 ?40 100 ?20 zse (lsb) 020406080 0.4 0.5 0.6 0.7 0.8 0.9 0.2 0.3 0.1 03224-012 r ab = 10k v dd = 3v v dd = 5v figure 12. zero-scale error temperature ( c) 0.16 0.04 ?55 115 ?35 ?15 supply current ( a) 5 25456585105 0.08 0.10 0.12 0.14 0.06 03224-013 v dd = 5.5v r ab = 10k figure 13. supply current vs. temperature input logic voltage (v) 10 0.0001 06 1 supply current (ma) 2345 0.001 0.01 0.1 1 03224-014 t a = 25 c r ab = 10k all digital pins tied together v dd = 5v v dd = 2.7v figure 14. supply current vs. digital input voltage
ad5273 rev. h | page 10 of 24 code (decimal) 500 400 300 200 100 ?300 06 4 8 rheostat mode tempco (ppm/ c) 16 24 32 40 48 56 0 ?100 ?200 03224-015 v dd = 5.5v t a = 25 c 1k 100k 50k 10k figure 15. rheostat mode tempco (?r wb /r wb )/?t vs. code code (decimal) 40 30 20 10 0 ?40 06 4 8 potentiometer mode tempco (ppm/c) 16 24 32 40 48 56 ?10 ?20 ?30 03224-016 v dd = 5.5v 1k? 10k? 10k? 10k? figure 16. potentiometer mode tempco (?v w /v w )/?t vs. code frequency (hz) 0 ?6 ?12 ?24 ?18 ?54 100 10m magnitude (db) 1k 10k 100k 1m ?30 ?42 ?36 ?48 03224-017 0x3f 0x20 0x10 0x08 0x02 0x01 0x00 0x04 figure 17. gain vs. frequency vs. code, r ab = 1 k frequency (hz) 0 ?6 ?12 ?24 ?18 ?54 100 1m magnitude (db) 1k 10k 100k ?30 ?42 ?36 ?48 03224-018 0x3f 0x20 0x10 0x08 0x04 0x02 0x01 0x00 figure 18. gain vs. frequency vs. code, r ab = 10 k frequency (hz) 0 ?6 ?12 ?24 ?18 ?54 100 1m magnitude (db) 1k 10k 100k ?30 ?42 ?36 ?48 03224-019 0x3f 0x20 0x10 0x08 0x04 0x02 0x01 0x00 figure 19. gain vs. frequency vs. code, r ab = 50 k frequency (hz) 0 ?6 ?12 ?24 ?18 ?54 100 1m magnitude (db) 1k 10k 100k ?30 ?42 ?36 ?48 03224-020 0x3f 0x20 0x10 0x08 0x04 0x02 0x01 0x00 figure 20. gain vs. frequency vs. code, r ab = 100 k
ad5273 rev. h | page 11 of 24 frequency (hz) 12 6 0 ?48 10m 100 magnitude (db) 1k 10k 100k 1m ?30 ?24 ?18 ?12 ?6 ?36 ?42 03224-021 1k 100k 50k 10k figure 21. ?3 db bandwidth frequency (hz) ? 80 0 100 1m 1k power supply rejection r a tio (db) 10k 100k ?20 ?40 ?60 03224-022 t a = 25c code = 0x20 v a = 2.5v, v b = 0v v dd = 5v dc 1.0v p-p ac v dd = 3v dc 0.6v p-p ac figure 22. psrr vs. frequency scl = 5v/div v w = 10mv/div v dd = 5.5v v a = 5.5v v b = gnd 10mv 5v 500ns 03224-023 f clk = 100khz figure 23. digital feedthrough scl = 5v/di v v dd = 5.5v v a = 5.5v v b = gnd f clk = 400khz data 0x00 0x3f 5v 5v 5 s v w = 5v/div 03224-024 figure 24. large settling time scl = 5v/div v w = 50mv/div v dd = 5.5v v a = 5.5v v b = gnd f clk = 100khz data 0x20 0x1f 5v 50mv 200ns 03224-025 figure 25. midscale glitch energy v dd = 5v/di v v w = 1v/div 5v 1v otp programmed at ms v dd = 5.5v v a = 5.5v r ab = 10k ? w 5s 03224-026 figure 26. power-up settling time after fuses blown
ad5273 rev. h | page 12 of 24 code (decimal) 10 1 0.01 06 4 03224-060 ch1 20.0ma ? m200ns a ch1 32.4ma t 588.000ns 1 8 theoretic a l i wb_max (ma) 16 24 32 40 48 56 0.1 03224-027 v a = v b = open t a = 25c r ab = 1k ? r ab = 10k ? r ab = 50k ? r ab = 100k ? figure 28. otp program energy plot for single fuse figure 27. i wb_max vs. code scl s d a ps p t 1 t 3 t 4 t 2 t 8 t 9 t 5 t 7 t 10 t 8 t 9 t 6 03224-028 figure 29. interface timing diagram
ad5273 rev. h | page 13 of 24 theory of operation the ad5273 is a one-time programmable (otp), set-and-forget, 6-bit digital potentiometer. the ad5273 allows unlimited 6-bit adjustments prior to the otp. otp technology is a proven cost- effective alternative over eemem in one-time memory program- ming applications. the ad5273 employs fuse link technology to achieve the memory retention of the resistance setting function. it comprises six data fuses, which control the address decoder for programming the rdac, one user mode test fuse for checking setup error, and one programming lock fuse for disabling any further programming once the data fuses are programmed correctly. one-time programming prior to otp activation, the ad5273 presets to midscale during power-on. after the wiper is set to the desired position, the resis- tance can be permanently set by programming the t bit and the one-time v dd_otp to high and by coding the part properly (see figure 31 ). to blow the fuses to achieve a given nonvolatile setting, the fuse link technology of the ad5273 requires a v dd_otp from 5 v to 5.5 v for the 1 k (dd8) and 10 k (dd9) options, or from 4.75 v to 5.25 v for the 50 k (dyg) and 100 k (dyh) options. during operation, however, v dd can be 2.7 v to 5.5 v. therefore, a system supply that is lower than v dd_otp requires an external supply for otp. the user is allowed only one attempt to blow the fuses. if the user fails to blow the fuses on the first attempt, the fuse structure may change such that they can never be blown, regardless of the energy applied during subsequent events. for details, see the power supply considerations section. the device control circuit has two validation bits, e1 and e0, that can be read back in the read mode to check the program- ming status, as shown in figure 32 . users should always read back the validation bits to ensure that the fuses are properly blown. after the fuses have been blown, all fuse latches are enabled upon subsequent power-on; therefore, the output corresponds to the stored setting. figure 30 shows a detailed functional block diagram. sda scl a w b fuses en dac reg. i 2 c interface comparator one-time program/test control block mux decoder fuse reg. 03224-031 figure 30. detailed fu nctional block diagram s010110ad00atx xxxxxxaxxd5d4d3d2d1d0ap slave address byte instruction byte data byte 03224-029 figure 31. sda write mode bit format s 0 1 0 1 1 0 ad0 1 a e1 e0 d5 d4 d3 d2 d1 d0 a p slave address byte data byte 03224-030 figure 32. sda read mode bit format sda bit definitions and descriptions s = start condition. p = stop condition. a = acknowledge. x = dont care. t = otp programming bit. logic 1 programs wiper position permanently. d5, d4, d3, d2, d1, d0 = data bits. e1, e0 = otp validation bits. 0, 0 = ready to program. 0, 1 = test fuse not blown successfully. (for factory setup checking purpose only. users should not see these combinations.) 1, 0 = fatal error. do not retry. discard the unit. 1, 1 = programmed successfully. no further adjustments possible. ad0 = i 2 c device address bit. allows maximum of two ad5273s to be addressed.
ad5273 rev. h | page 14 of 24 variable resistance and voltage for rheostat mode if only the w-to-b or w-to-a terminals are used as variable resistors, the unused a or b terminal can be opened or shorted with w. this operation is called rheostat mode (see figure 33 ). 03224-032 a w b a w b a w b figure 33. rheostat mode configuration the nominal resistance, r ab , of the rdac has 64 contact points accessed by the wiper terminal, plus the b terminal contact if r wb is considered. the 6-bit data in the rdac latch is decoded to select one of the 64 settings. assuming that a 10 k part is used, the wipers first connection starts at terminal b for data register 0x00. this connection yields a minimum of 60 resistance between terminal w and terminal b because of the 60 wiper contact resistance. the second connection is the first tap point, which corresponds to 219 (r w = 1 r ab /63 + r w ) for data register 0x01, and so on. each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,060 (63 r ab /63 + r w ). figure 34 shows a simplified diagram of the equivalent rdac circuit. the general equation determining r wb is () w ab wb rr d dr += 63 (1) where: d is the decimal equivalent of the 6-bit binary code. r ab is the end-to-end resistance. r w is the wiper resistance contributed by the on resistance of the internal switch. table 4. r wb vs. codes; r ab = 10 k; terminal a opened d (dec) r wb () output state 63 10,060 full scale (r ab + r w ) 32 5139 midscale 1 219 1 lsb 0 60 zero scale (wiper contact resistance) because a finite wiper resistance of 60 is present in the zero- scale condition, care should be taken to limit the current flow between w and b in this state to a maximum pulse current of 20 ma. otherwise, degradation or possible destruction of the internal switch contact can occur. similar to the mechanical potentiometer, the resistance of the rdac between the wiper w and terminal a also produces a complementary resistance, r wa . when these terminals are used, terminal b can be opened or shorted to w. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. the general equation for this operation is () w ab wa rr d dr + ? = 63 63 (2) table 5. r wa vs. codes; r ab =10 k; terminal b opened d (dec) r wa () output state 63 60 full scale 32 4980 midscale 1 9901 1 lsb 0 10,060 zero scale the typical distribution of the resistance tolerance from device to device is process-lot dependent, and it is possible to have 30% tolerance. d5 d4 d3 d2 d1 d0 rdac latch and decoder r s r s r s a w b 03224-033 figure 34. ad5273 equivalent rdac circuit variable resistance and voltage for potentiometer mode if all three terminals are used, the operation is called the potentiometer mode. the most common configuration is the voltage divider operation (see figure 35 ). a v i w b v o 03224-034 figure 35. potentiometer mode configuration ignoring the effect of the wiper resistance, the transfer function is simply () a w v d dv 63 = (3) a more accurate calculation, which includes the wiper resistance effect, yields () a w ab w ab w v rr rr d dv 2 63 + + = (4)
ad5273 rev. h | page 15 of 24 unlike rheostat mode where the absolute tolerance is high, potentiometer mode yields an almost ratiometric function of d/63 with a relatively small error contributed by the r w terms. therefore, the tolerance effect is almost cancelled. although the step resistor, r s , and cmos switch resistor, r w , have very differ- ent temperature coefficients, the ratiometric adjustment also reduces the overall temperature coefficient effect to 5 ppm/c, except at low value codes where r w dominates. potentiometer mode includes op amp feedback resistor networks and other voltage scaling applications. terminal a, terminal w, and terminal b can in fact be input or output terminals, provided that |v ab |, |v wa |, and |v wb | do not exceed v dd to gnd. esd protection digital inputs sda and scl are protected with a series input resistor and parallel zener esd structures (see figure 36 ). logic 340 03224-035 figure 36. esd protection of digital pins terminal voltage operating range there are also esd protection diodes between v dd and the rdac terminals. the v dd of ad5273 therefore defines their voltage boundary conditions (see figure 37 ). supply signals pres e nt on ter m in a l a , ter mi na l b, and ter m in a l w t hat exce e d v dd are clamped by the internal forward-biased diodes. gnd a w b v dd 03224-036 figure 37. maximum terminal voltages set by v dd power-up/power-down sequences because of the esd protection diodes, it is important to power v dd first before applying any voltages to terminal a, terminal b, and terminal w. otherwise, the diode is forward-biased such that v dd is powered unintentionally and can affect the rest of the users circuits. the ideal power-up sequence is in the following order: gnd, v dd , digital inputs, and v a /v b /v w . the order of powering v a , v b , v w , and digital inputs is not important as long as they are powered after v dd . similarly, v dd should be powered down last. power supply considerations to minimize the package pin count, both otp and normal opera- ting voltage supplies are applied to the same v dd terminal of the ad5273. the ad5273 employs fuse link technology that requires from 5 v to 5.5 v for the 1 k (dd8) and 10 k (dd9) options, or from 4.75 v to 5.25 v for the 50 k (dyg) and 100 k (dyh) options, for blowing the internal fuses to achieve a given setting, but normal v dd can be in the range of 2.7 v to 5.5 v after completing the fuse programming process. as a result, dual voltage supplies and isolation are needed if the system v dd is outside the required v dd_otp range. for successful otp, the fuse programming supply (either an on-board regulator or rack-mount power supply) must be rated at 5 v to 5.5 v for the 1 k (dd8) and 10 k (dd9) options, or at 4.75 v to 5.25 v for the 50 k (dyg) and 100 k (dyh) options, and be capable of sourcing 100 ma for 400 ms. when fuse programming is completed, the v dd_otp supply can be removed to allow normal operation of 2.7 v to 5.5 v; the device then reduces the current consumption to the a range. when operating systems at 2.7 v, use of the bidirectional low threshold p-ch mosfets is recommended for the supplys isolation. as shown in figure 38 , this assumes that the 2.7 v system voltage is applied first and that the p1 and p2 gates are pulled to ground, thus turning on p1 first and then p2. as a result, v dd of the ad5273 approaches 2.7 v. when the ad5273 setting is found, the factory tester applies the v dd_otp to both the v dd and the mosfets gates, thus turning off p1 and p2. the otp command should be executed at this time to program the ad5273 while the 2.7 v source is protected. once the fuse programming is complete, the tester withdraws the v dd_otp and the ad5273s setting is fixed permanently. ad5273 v dd c2 0.1f a pplies for otp only c1 10mf r1 10k ? 2.7v v dd_otp p1 p2 p1 = p2 = fdv302p, nds0610 03224-039 figure 38. otp supply isolated from the 2.7 v normal operating supply the ad5273 achieves the otp function through blowing internal fuses. users should always apply the recommended otp programming voltage at the first fuse programming attempt. failure to comply with this requirement can lead to a change in fuse structures, rendering programming inoperable. care should be taken when scl and sda are driven from a low voltage logic controller. users must ensure that the logic high level is between 0.7 v dd and v dd . refer to the level shift for different voltages operation section. poor pcb layout introduces parasitics that can affect fuse program- ming. therefore, it is recommended to add a 10 f tantalum capacitor in parallel with a 1 nf ceramic capacitor as close as possible to the v dd pin. the type and value chosen for both capaci- tors are important. this combination of capacitor values provides a fast response and larger supply current handling with minimum supply drop during transients. as a result, these capacitors increase the otp programming success by not inhibiting the proper energy needed to blow the internal fuses. additionally, c1 minimizes transient disturbance and low frequency ripple, while c2 reduces high frequency noise during normal operation.
ad5273 rev. h | page 16 of 24 controlling the ad5273 to control the ad5273, users can program the device with either computer software or with external i 2 c controllers. software programming because of the otp feature, users can program the ad5273 in the factory before shipping it to end users. therefore, analog devices offers device programming software that can be imple- mented in the factory on computers running windows nt, windows 2000, and windows xp platforms. the software, which can be downloaded from the ad5273 product page at www.analog.com , is an executable file that does not require any programming languages or user programming skills. figure 39 shows the software interface. 03224-040 figure 39. software interface write the ad5273 starts at midscale after power-up prior to any otp programming. to increment or decrement the resistance, move the scrollbar on the left. once the desired setting is found, click program permanent to lock the setting permanently. to write any specific values, use the bit pattern control in the upper section and click run . the format of writing data to the device is shown in figure 31 . once the desired setting is found, set the t bit to 1 and click run to program the setting permanently. read to read the validation bits and data from the device, click read . the user can also set the bit pattern in the upper section and click run . the format of reading data from the device is shown in figure 32 . to control the device in both read and write operations, the program generates the i 2 c digital signals through the parallel port lpt1 pin 2, pin 3, pin 15, and pin 25 for sda_write, scl, sda_read, and dgnd, respectively (see figure 40 ). to apply the device programming software in the factory, lay out the ad5273 scl and sda pads on the pcb such that the programming signals can be communicated to and from the parallel port (see figure 40 ). figure 41 shows a recommended ad5273 pcb layout into which pogo pins can be inserted for factory programming. to prevent damaging the pc parallel port, 100 resistors should also be put in series to the scl and sda pins. pull-up resistors on scl and sda are also required. 03224-041 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 scl r3 100 r1 100 r2 100 sda read write r4 10k r5 10k v dd figure 40. parallel port connection; pin 2 = sda_write, pin 3 = scl, pin 15 = sda_read, and pin 25 = dgnd w v dd gnd scl a b ad0 sda 03224-042 figure 41. recommended ad5273 pcb layout
ad5273 rev. h | page 17 of 24 i 2 c controller programming write bit patterns ack. by ad5273 ack. by ad5273 ack. by ad5273 sda frame 1 slave address byte scl stop by master s tart b y master 0 0 1 0 11 0 ad0 r/w 0 x x x x x x x x xd5 d4 d3 d2 d1 d0 80 80 8 frame 2 instruction byte frame 1 data byte 03224-043 figure 42. writing to the rdac register ack. by ad5273 ack. by ad5273 ack. by ad5273 frame 1 slave address byte stop by master s tart b y master frame 2 instruction byte frame 1 data byte 03224-044 sda scl 0 0 1 0 11 0 ad0 r/w 1 x x x x x xx x x d5d4d3d2d1 d0 8 0 8 08 figure 43. activating one-time programming read bit pattern ack. by ad5273 no ack. by ad5273 frame 1 slave address byte stop by master s tart b y master frame 2 data byte from selected rdac register 03224-059 sda scl 0 1 0 11 0 ad0 r/w e1 e0 d5 d4 d3 d2 d1 d0 0 8 08 figure 44. reading data from the rdac register for users who do not use the software solution, the ad5273 can be controlled via an i 2 c-compatible serial bus and is connected to this bus as a slave device. referring to figure 42 , figure 43 , and figure 44 , the 2-wire i 2 c serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition. a start condition is defined as a high-to-low transition on the sda line while scl is high, as shown in figure 42 . the byte following the start condition is the slave address byte, which consists of six msbs defined as 010110. the next bit is ad0; it is an i 2 c device address bit. depending on the states of the ad0 bits, two ad5273s can be addressed on the same bus, as shown in figure 45 . the last lsb is the r/ w bit, which determines whether data is read from or written to the slave device. the slave address corresponding to the transmitted address responds by pulling the sda line low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. 2. a write operation contains one more instruction byte than the read operation. the instruction byte in the write mode follows the slave address byte. the msb of the instruction byte labeled t is the otp bit. after acknowledging the instruction byte, the last byte in the write mode is the data byte. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowl- edge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl, as shown in figure 42 . 3. in read mode, the data byte follows immediately after the acknowledgment of the slave address byte. data is trans- mitted over the serial bus in sequences of nine clock pulses (slight difference from write mode, there are eight data bits followed by a no acknowledge bit). similarly, the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl, as shown in figure 44 .
ad5273 rev. h | page 18 of 24 4. when all data bits have been read or written, a stop con- dition is established by the master. a stop condition is defined as a low-to-high transition on the sda line while scl is high. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition, as shown in figure 42 and figure 43 . in read mode, the master issues a no acknowledge for the ninth clock pulse, that is, the sda line remains high. the master then brings the sda line low before the 10 th clock pulse, which goes high to establish a stop condition, as shown in figure 44 . a repeated write function gives the user flexibility to update the rdac output continuously, except after permanent programming, when the part is addressed and receives instructions only once. during the write cycle, each data byte updates the rdac output. for example, after the rdac has acknowledged its slave address and instruction bytes, the rdac output updates after these two bytes. if another byte is written to the rdac while it is still addressed to a specific slave device with the same instruc- tion, this byte updates the output of the selected slave device. if different instructions are needed, the write mode must be started again with a new slave address, instruction, and data bytes. similarly, a repeated read function of the rdac is also allowed. controlling two devices on one bus figure 45 shows two ad5273 devices on the same serial bus. each has a different slave address because the state of each ad0 pin is different. this allows each device to operate independently. the master device output bus line drivers are open-drain pull- down in a fully i 2 c-compatible interface. master sda scl ad0 ad5273 sda scl ad0 ad5273 sda scl 5 v r p r p 5v 03224-045 figure 45. two ad5273 devices on one bus
ad5273 rev. h | page 19 of 24 applications information dac it is common to buffer the output of the digital potentiometer as a dac. the buffer minimizes the load dependence and delivers higher current to the load, if needed. gnd v in v out 1u1 5v 2 3 v o ad8601 5v a w b adr03 u3 ad5273 u2 03224-046 figure 46. programmable voltage reference (dac) programmable voltage source with boosted output for applications that require high current adjustment, such as a laser diode driver or tunable laser, consider a booster voltage source, as shown in figure 47 . +v w signal c c r bias ld v in a b v out u1 ad5273 u3 2n7002 ad8601 u2 ?v i l 03224-047 figure 47. programmable booster voltage source in this circuit, the inverting input of the op amp forces the v out to be equal to the wiper voltage set by the digital potenti- ometer. the load current is then delivered by the supply via the n-channel fet, n 1 . n 1 power handling must be adequate to dissipate (v in ? v out ) i l power. this circuit can source a max- imum of 100 ma with a 5 v supply. for precision applications, a voltage reference, such as the adr421 , adr03 , or adr370 , can be applied at terminal a of the digital potentiometer. programmable current source a programmable current source can be implemented with the circuit shown in figure 48 . the load current is the voltage across terminal b to terminal w of the ad5273 divided by r s . at zero scale, terminal a of the ad5273 is ?2.048 v, which makes the wiper voltage clamped at ground potential. depending on the load, equation 5 is therefore valid only at certain codes. for example, when the compliance voltage, v l , equals half of v ref , the current can be programmed from midscale to full scale of the ad5273. i l gnd v s 2u1 5 v 4 6 3 sleep 0v to ... ouput ref191 c1 1f b a w r s 102 ? 100 ? r l v l ?2.048 + v l ?5v op1177 +5v v+ v? u2 u3 ad5273 03224-048 figure 48. programmable current source ( ) 6332| 64/ ? = d r dv i s ref l (5) gain control compensation as shown in figure 49 , the digital potentiometers are commonly used in gain controls or sensor transimpedance amplifier signal conditioning applications. u1 c2 4.7pf a b w v o v i c1 r1 47k r2 100k 03224-049 figure 49. typical noninverting gain amplifier in both applications, one of the digital potentiometer terminals is connected to the op amp inverting node with finite terminal capacitance, c1. it introduces a zero for the 1 o term with 20 db/dec, whereas a typical op amp gbp has ?20 db/dec characteristics. a large r2 and finite c1 can cause this zeros frequency to fall well below the crossover frequency. therefore, the rate of closure becomes 40 db/dec and the system has a 0 phase margin at the crossover frequency. the output may ring, or in the worst case, oscillate when the input is a step function. similarly, it is also likely to ring when switching between two gain values because this is equivalent to a step change at the input. to reduce the effect of c1, users should also configure terminal b or terminal a rather than terminal w at the inverting node.
ad5273 rev. h | page 20 of 24 depending on the op amp gbp, reducing the feedback resistor may extend the zeros frequency far enough to overcome the problem. a better approach is to include a compensation capacitor, c2, to cancel the effect caused by c1. optimum compensation occurs when r1 c1 = r2 c2, but this is not an option because of the variation of r2. as a result, users can use the relationship described and scale c2 as if r2 were at its maximum value. however, doing so may overcompensate by slowing down the settling time when r2 is set to low values. to avoid this problem, c2 should be found empirically for a given application. in general, setting c2 in the range of a few picofarads to no more than a few tenths of a picofarad is usually adequate for compensation. there is also a terminal w capacitance connected to the output (not shown); its effect on stability is less significant; therefore, compensation is not necessary unless the op amp is driving a large capacitive load. programmable low-pass filter in adc applications, it is common to include an antialiasing filter to band-limit the sampling signal. to minimize various system redesigns, users can use two 1 k ad5273s to construct a generic second-order sallen-key low-pass filter. because the ad5273 is a single-supply device, the input must be dc offset when an ac signal is applied to avoid clipping at ground. this is illustrated in figure 50 . the design equations are 2 2 2 o o o i o s q s v v + + = (6) 1r2c1c2r o 1 = (7) r2c2 r1c1 q 11 += (8) users can first select some convenient values for the capacitors. to achieve maximally flat bandwidth where q = 0.707, let c1 be twice the size of c2 and let r1 = r2. as a result, r1 and r2 can be adjusted to the same setting to achieve the desired bandwidth. v o ad8601 +2.5v u1 ?2.5v v+ v? c1 c r1 r2 a b w a b w c2 c adjusted to same settings v i 03224-050 figure 50. sallen key low-pass filter level shift for different voltages operation if the scl and sda signals come from a low voltage logic controller and are below the minimum v ih level (0.7 v dd ), level-shift the signals for successful read/write communication between the ad5273 and the controller. figure 51 shows one of the implementations. for example, when sda1 is 2.5 v, m1 turns off, and sda2 becomes 5 v. when sda1 is 0 v, m1 turns on, and sda2 approaches 0 v. as a result, proper level-shifting is established. m1 and m2 should be low threshold n-channel power mosfets, such as fdv301n. 2.5v controller 2.7v?5.5v ad5273 rp rp rp rp v dd1 = 2.5v v dd2 = 5 v g g s d m1 s d m2 s da1 s cl1 sda2 scl2 03224-051 figure 51. level shift for different voltages operation rdac circuit simulation model the internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the digital potentio- meters. configured as a potentiometer divider, the ?3 db bandwidth of the ad5273 (1 k resistor) measures 6 mhz at half scale. figure 17 to figure 20 provide the large signal bode plot characteristics of the four available resistor versions: 1 k, 10 k, 50 k, and 100 k. figure 52 shows a parasitic simula- tion model. the code following figure 52 provides a macro model net list for the 1 k device. 55pf c a 2 5pf c b 25pf ab 1k w c w 03224-055 figure 52. circuit simulation model for rdac = 1 k macro model net list for rdac .param d = 63, rdac = 1e3 * .subckt dpot (a,w,b) * ca a 0 25e-12 rwa a w {(1-d/63)*rdac+60} cw w 0 55e-12 rwb w b {d/63*rdac+60} cb b 0 25e-12 * .ends dpot
ad5273 rev. h | page 21 of 24 evaluation board w v dd gnd scl scl sda a 8 7 1 2 3 4 8 7 6 5 6 5 4 3 2 1 b ad0 c1 10mf c9 10f c4 0.1f c8 0.1f c2 0.1f c3 0.1f c5 0.1f r1 10k ? r2 10k ? sda temp gnd v in trim v out v ref v dd v cc v ee agnd jp2 jp1 out1 jp8 a wv in b w v dd gnd scl a b ad0 sda c7 10f c6 0.1f v dd v dd j1 u1 u4 ad5170 adr03 ad5171/ad5273 1 2 3 4 6 7 5 2 8 1 4 3 8 7 6 5 1 2 3 5 4 u2 u3a u3b cp3 cp5 cp1 cp4 cp2 jp7 +in1 v+ +in2 out2 out1 ?in1 ?in1 ?in2 v? jp4 jp6 jp5 jp3 cp6 cp7 03224-056 figure 53. evaluation board schematic v ref v ref v o out1 ad822 a 2 3 b 11 1 jp4 w a b u2 w v+ v? jp2 jp1 jp7 v dd cp2 jp3 u3a 4 03224-057 figure 54. one possible configuration programmable voltage reference 03224-058 figure 55. evaluation board
ad5273 rev. h | page 22 of 24 outline dimensions compliant to jedec standards mo-178-ba 121608-a 8 4 0 seating plane 1.95 bsc 0.65 bsc 0.60 bsc 76 1234 5 3.00 2.90 2.80 3.00 2.80 2.60 1.70 1.60 1.50 1.30 1.15 0.90 0 .15 max 0 .05 min 1.45 max 0.95 min 0.22 max 0.08 min 0.38 max 0.22 min 0.60 0.45 0.30 pin 1 indicator 8 figure 56. 8-lead small outline transistor package [sot-23] (rj-8) dimensions shown in millimeters ordering guide model 1 , 2 r ab (k) temperature range package option package description ordering quantity branding ad5273brjz1-r2 1 ?40c to +105c rj-8 8-lead sot-23 250 dd8 ad5273brjz1-reel7 1 ?40c to +105c rj-8 8-lead sot-23 3,000 dd8 ad5273brjz10-r2 10 ?40c to +105c rj-8 8-lead sot-23 250 dd9 ad5273brjz10-r7 10 ?40c to +105c rj-8 8-lead sot-23 3,000 dd9 ad5273brjz50-reel7 50 ?40c to +105c rj-8 8-lead sot-23 3,000 dyg ad5273brjz100-r2 100 ?40c to +105c rj-8 8-lead sot-23 250 dyh AD5273BRJZ100-R7 100 ?40c to +105c rj-8 8-lead sot-23 3,000 dyh ad5273eval evaluation board 1 z = rohs compliant part. 2 for the evaluation board, users should order samples because the evaluation kit comes with a socket, but does not include the parts.
ad5273 rev. h | page 23 of 24 notes
ad5273 rev. h | page 24 of 24 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ?2002C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d03224-0-10/10(h)

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